View LT3796_4613145.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

lt3761 1 3761f typical a pplica t ion fea t ures a pplica t ions descrip t ion 60v in led controller with internal pwm generator the lt ? 3761 is a dc/dc controller designed to operate as a constant-current source and constant-voltage regulator. it features a programmable internal pwm dimming signal. the lt3761 is ideally suited for driving high current leds, but also has features to make it suitable for charging bat- teries and supercapacitors. the fixed frequency, current mode architecture results in stable operation over a wide range of supply and output voltages. a voltage feedback pin serves as the input for several led protection features, and also makes it possible for the converter to operate as a constant-voltage source. a frequency adjust pin allows the user to program the frequency from 100khz to 1mhz to optimize efficiency, performance or external component size. the lt3761 senses output current at the high side or at the low side of the load. the pwm input can be configured to self-oscillate at fixed frequency with duty ratio program- mable from 4% to 96%. when driven by an external signal, the pwm input provides led dimming ratios of up to 3000:1. the ctrl input provides additional analog dimming capability. l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks and true color pwm is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents including 7199560, 7321203. 94% efficient boost led driver for automotive headlamp with 25:1 internal pwm dimming pwm dimming waveforms at various dim voltage settings n 3000:1 true color pwm? dimming for leds n wide v in range: 4.5v to 60v n rail-to-rail current sense range: 0v to 80v n programmable pwm dimming signal generator n constant current (3%) and constant-voltage (2%) regulation n analog dimming n drives leds in boost, sepic, inverting, buck mode, buck-boost mode, or flyback configuration n output short-circuit protected boost n open led protection and reporting n adjustable switching frequency: 100khz to 1mhz n programmable v in uvlo with hysteresis n c/10 indication for battery chargers n low shutdown current: <1a n thermally enhanced 16-lead msop package n high voltage led strings >100v with ground referred current sense n grounded anode leds n battery and supercap chargers n accurate current limited voltage regulators v in lt3761 10h rt v c intv cc en/uvlo fb v ref sense 1m 100k intv cc intv cc 499k 2.2f 2 4.7nf 0.01f 47nf 300hz 2.2f 4 v in 8v to 60v 124k 90.9k 5.1k 28.7k 350khz 1f 140k ctrl 10m 1m 16.9k 60w led string 3761 ta01a openled dim/ss dim pwm gnd isp isn gate pwmout 0.25 1a i led 1a/div 0.5ms/div v dim = 7.7v dc pwm = 96% v dim = 4v dc pwm = 50% v dim = 1.5v dc pwm = 10% v dim = 0.4v dc pwm = 4.3% 3761 ta01b
lt3761 2 3761f o r d er i n f orma t ion lead free finish tape and reel part marking* package description temperature range lt3761emse#pbf lt3761emse#trpbf 3761 16-lead plastic msop C40c to 125c lt3761imse#pbf lt3761imse#trpbf 3761 16-lead plastic msop C40c to 125c lt3761hmse#pbf lt3761hmse#trpbf 3761 16-lead plastic msop C40c to 150c consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. consult ltc marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ p in c on f igura t ion a bsolu t e m aximum r a t ings v in , en/uvlo ............................................................ 6 0v isp, isn ..................................................................... 8 0v intv cc ................................................... v in + 0.3v, 9.6v gate, pwmout ................................................ ( note 2) ctrl, openled ........................................................ 15 v fb, pwm .................................................................. 9. 6v v c , v ref ...................................................................... 3v rt, d im/ss .............................................................. 1. 5v sense ...................................................................... 0. 5v operating ambient temperature range (notes 3, 4) lt3761e ................................................. C 40 to 125c lt3761i .................................................. C4 0 to 125c lt3761h ................................................ C 40 to 150c storage temperature range .................. C 65c to 150c (note 1) 1 2 3 4 5 6 7 8 pwmout fb isn isp v c ctrl v ref pwm 16 15 14 13 12 11 10 9 gate sense v in intv cc en/uvlo rt dim/ss openled top view mse package 16-lead plastic msop 17 gnd t jmax = 125c (e-, i-grades), t jmax = 150c (h-grade), ja = 43c/w, jc = 4c/w exposed pad (pin 17) is gnd, must be soldered to pcb the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v in = 24v, en/uvlo = 24v, ctrl = 2v, pwm = 5v, unless otherwise noted. e lec t rical c harac t eris t ics parameter conditions min typ max units v in minimum operating voltage v in tied to intv cc l 4.5 v v in shutdown i q en/uvlo = 0v, pwm = 0v en/uvlo = 1.15v, pwm = 0v 0.1 1 6 a a v in operating i q (not switching) pwm = 0v 1.8 2.2 ma v ref voltage C100a i vref 0a l 1.955 2.02 2.05 v v ref line regulation 4.5v v in 60v 0.001 %/v v ref pull-up current v ref = 0v l 150 185 210 a sense current limit threshold l 98 105 118 mv sense input bias current current out of pin, sense = 0v 40 a dim/ss pull-up current current out of pin, dim/ss = 0v l 10 12 14 a dim/ss voltage clamp i dim/ss = 0a 1.2 v
lt3761 3 3761f the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v in = 24v, en/uvlo = 24v, ctrl = 2v, pwm = 5v, unless otherwise noted. e lec t rical c harac t eris t ics parameter conditions min typ max units error amplifier full-scale isp/isn current sense threshold (v isp-isn ) ctrl 1.2v, isp = 48v ctrl 1.2v, isn = 0v l l 242 243 250 257 258 268 mv mv 1/10th scale isp/isn current sense threshold (v isp-isn ) ctrl = 0.2v, isp = 48v ctrl = 0.2v, isn = 0v l l 21 20 25 28 30 36 mv mv mid-scale isp/isn current sense threshold (v isp-isn ) ctrl = 0.5v, isp = 48v ctrl = 0.5v, isn = 0v l l 96 95 100 105 104 115 mv mv isp/isn overcurrent threshold 600 mv isp/isn current sense amplifier input common mode range (v isn ) 0 80 v isp/isn input bias current high side sensing (combined) pwm = 5v (active), isp = isn = 48v pwm = 0v (standby), isp = isn = 48v 100 0.1 a a isp/isn input bias current low side sensing (combined) pwm = 5v, isp = isn = 0v C230 a isp/isn current sense amplifier g m (high side sensing) v isp-isn = 250mv, isp = 48v 120 s isp/isn current sense amplifier g m (low side sensing) v isp-isn = 250mv, isn = 0v 70 s ctrl pin range for linear current sense threshold adjustment l 0 1.0 v ctrl input bias current current out of pin 50 100 na v c output impedance 0.9v v c 1.5v 15 m v c standby input bias current pwm = 0v C20 20 na fb regulation voltage (v fb ) isp = isn = 48v, 0v l 1.225 1.255 1.275 v fb amplifier g m fb = v fb , isp = isn = 48v 500 s fb pin input bias current current out of pin, fb = v fb 40 100 na fb open led threshold openled falling, isp tied to isn l v fb C 65mv v fb C 50mv v fb C 40mv v c/10 inhibit for openled assertion (v isp-isn ) fb = v fb , isn = 48v, 0v 14 25 39 mv fb overvoltage threshold pwmout falling v fb + 50mv v fb + 60mv v fb + 70mv v v c current mode gain (?v vc /?v sense ) 4 v/v oscillator switching frequency r t = 95.3k r t = 8.87k l 85 925 100 1000 115 1050 khz khz gate minimum off-time c gate = 2200pf 160 ns gate minimum on-time c gate = 2200pf 180 ns linear regulator intv cc regulation voltage 10v v in 60v l 7.6 7.85 8.05 v intv cc maximum operating voltage 8.1 v intv cc minimum operating voltage 4.5 v dropout (v in C intv cc ) i intvcc = C10ma, v in = 7v 390 mv intv cc undervoltage lockout l 3.9 4.1 4.4 v intv cc current limit intv cc = 6v, 8v v in 60v 30 36 42 ma intv cc current in shutdown en/uvlo = 0v, intv cc = 8v 8 13 a
lt3761 4 3761f e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v in = 24v, en/uvlo = 24v, ctrl = 2v, pwm = 5v, unless otherwise noted. parameter conditions min typ max units logic inputs/outputs en/uvlo threshold voltage falling l 1.18 1.220 1.26 v en/uvlo rising hysteresis 20 mv en/uvlo input low voltage i vin drops below 1a 0.4 v en/uvlo pin bias current low en/uvlo = 1.15v l 1.7 2.3 2.7 a en/uvlo pin bias current high en/uvlo = 1.33v 10 100 na openled output low i openled = 1ma 200 mv pwm pin signal generator pwm falling threshold l 0.78 0.83 0.88 v pwm threshold hysteresis (v pwmhys ) i dim/ss = 0a 0.35 0.4 0.6 v pwm pull-up current (i pwmup ) pwm = 0.7v, i dim/ss = 0a 6 7.5 9 a pwm pull-down current (i pwmdn ) pwm = 1.5v, i dim/ss = 0a 68 88 110 a pwm fault mode pull-down current intv cc = 3.8v 1.5 ma pwmout duty ratio for pwm signal generator (note 5) i dim/ss = C6.5a i dim/ss = 0a i dim/ss = 21.5a i dim/ss = 52a 3.1 6.8 40 95 4.1 7.9 47.8 96.5 5.2 9.2 56 98 % % % % pwmout signal generator frequency pwm = 47nf to gnd, i dim/ss = 0a 215 300 435 hz pwmout, gate pin drivers pwmout driver output rise time (t r ) c l = 560pf 35 ns pwmout driver output fall time (t f ) c l = 560pf 35 ns pwmout output low (v ol ) pwm = 0v 0.05 v pwmout output high (v oh ) intv cc C 0.05 v gate output rise t ime (t r ) c l = 3300pf 25 ns gate output fall time (t f ) c l = 3300pf 25 ns gate output low (v ol ) 0.1 v gate output high (v oh ) intv cc C 0.05 v note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: do not apply a positive or negative voltage or current source to gate or pwmout pins, otherwise permanent damage may occur. note 3: the lt3761e is guaranteed to meet performance specifications from the 0c to 125c junction temperature. specifications over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the lt3761i is guaranteed over the full C40c to 125c operating junction temperature range. the lt3761h is guaranteed over the full C40c to 150c operating junction temperature range. operating lifetime is derated at junction temperatures greater than 125c. note 4: the lt3761 includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed the maximum operating junction temperature when overtemperature protection is active. continuous operation above the specified maximum junction temperature may impair device reliability. note 5: pwmout duty ratio is calculated: duty = i pwmup /(i pwmup + i pwmdn )
lt3761 5 3761f typical p er f ormance c harac t eris t ics fb regulation voltage (v fb ) vs temperature v isp-isn threshold vs fb voltage v ref source current vs temperature v ref voltage vs temperature switching frequency vs r t switching frequency vs temperature v isp-isn threshold vs ctrl voltage v isp-isn threshold vs isp voltage full-scale v isp-isn threshold vs temperature t a = 25c, unless otherwise noted. ctrl voltage (v) 0 ?50 v isp-isn threshold (mv) 50 150 250 0.5 1 1.5 300 0 100 200 2 3761 g01 244 246 250 260 256 254 258 248 252 3761 g03 v isp-isn (mv) temperature (c) ?50 0 50 75 ?25 25 100 150125 ctrl = 2v isp = 48v isn = 0 3761 g04 v fb (v) temperature (c) 1.240 1.250 1.265 1.260 1.270 1.245 1.255 ?50 0 50 75 ?25 25 100 150125 3761 g06 v ref source current (a) temperature (c) 150 160 190 180 200 170 ?50 0 50 75 ?25 25 100 150125 3761 g07 v ref (v) temperature (c) 1.98 2.00 2.02 2.06 2.05 2.04 1.99 2.01 2.03 ?50 0 50 75 ?25 25 100 150125 3761 g09 frequency (khz) temperature (c) 380 390 400 420 415 410 385 395 405 ?50 0 50 75 ?25 25 100 150125 r t = 25.5k r t (k) switching frequency (khz) 3761 g08 10 100 100 200 400 600 1000 900 800 300 500 700 isp voltage (v) 240 v isp-isn threshold (mv) 250 260 245 255 3761 g02 0 20 40 60 80 3761 g05 v isp-isn (mv) fb voltage (v) 0 100 250 200 300 50 150 1.20 1.22 1.23 1.21 1.24 1.261.25 ctrl = 2v ctrl = 0.5v
lt3761 6 3761f typical p er f ormance c harac t eris t ics intv cc current limit vs vs temperature intv cc dropout voltage vs current, temperature v isp-isn c/10 threshold vs temperature sense current limit threshold vs temperature en/uvlo hysteresis current vs temperature en/uvlo threshold vs temperature t a = 25c, unless otherwise noted. pwm signal generator duty ratio vs dim/ss current pwm signal generator frequency vs duty ratio 3761 g10 sense threshold (mv) temperature (c) 90 100 110 95 105 ?50 0 50 75 ?25 25 100 150125 3761 g11 en/uvlo current (a) temperature (c) 1.8 2.0 2.6 2.4 2.8 2.2 ?50 0 50 75 ?25 25 100 150125 3761 g12 en/uvlo threshold (v) temperature (c) 1.19 1.23 1.27 1.21 1.25 ?50 0 50 75 ?25 25 100 150125 falling rising 3761 g13 intv cc current limit (ma) temperature (c) 30 34 40 32 36 38 ?50 0 50 75 ?25 25 100 150125 ldo current (ma) 3761 g14 0 5 10 15 2520 30 ?1.8 ?1.2 ?1.4 ?1.6 ?0.8 ?0.4 ?0.6 0 ?1.0 ?0.2 ldo dropout (v) t a = ?45c v in = 7v t a = 130c t a = 25c pwmout waveform 200ns/div pwm input pwmout 5v/div 3761 g18 c pwmout = 2.2nf dim/ss current (a) ?10 pwmout duty ratio (%) 100 60 20 80 40 0 20 40 10 30 0 3761 g16 50 duty ratio (%) 0 pwmout frequency (hz) 340 280 320 300 260 6040 80 20 3761 g17 100 c pwm = 47nf 3761 g15 v isp-isn (mv) temperature (c) 10 15 30 25 35 20 ?50 0 50 75 ?25 25 100 150125 isp = 24v isn = 0v
lt3761 7 3761f typical p er f ormance c harac t eris t ics t a = 25c, unless otherwise noted. isp/isn input bias current vs ctrl voltage, isn = 0v pwmout duty ratio vs temperature, i dim/ss = 21.5a v isp-isn overcurrent threshold vs temperature pwmout duty ratio vs temperature, i dim/ss = 0a isp/isn input bias current vs ctrl voltage, isp = 48v dim/ss voltage vs current, temperature ctrl (v) 0 input bias current (a) 40 120 100 80 20 60 3761 g20 0 0.5 1 1.5 2 isp isn ctrl (v) ?200 input bias current (a) ?120 0 ?40 ?160 ?80 3761 g21 0 0.5 1 1.5 2 isp isn dim/ss current (a) 3761 g19 ?10 0 10 20 4030 50 1.10 1.15 1.30 1.20 1.25 dim/ss voltage (v) t a = ?45c, 25c t a = 130c 6.5 7.0 8.0 9.5 9.0 7.5 8.5 3761 g22 duty ratio (%) temperature (c) ?50 0 50 75 ?25 25 100 150125 c pwm = 47nf 45 49 55 53 47 51 3761 g23 duty ratio (%) temperature (c) ?50 0 50 75 ?25 25 100 150125 c pwm = 47nf 3761 g24 v isp-isn (mv) temperature (c) 300 400 700 600 800 500 ?50 0 50 75 ?25 25 100 150125 isp = 24v isn = 0v
lt3761 8 3761f pwmout (pin 1): buffered version of pwm signal for driving led load disconnect nmos or level shift. this p in also serves in a protection function for the fb over - voltage conditionwill toggle if the fb input is greater than the fb regulation voltage (v fb ) plus 60mv (typical). the pwmout pin is driven from intv cc . use of a fet with gate cut-off voltage higher than 1v is recommended. fb (pin 2): voltage loop feedback pin. fb is intended for constant-voltage regulation or for led protection and open led detection. the internal transconductance amplifier with output v c will regulate fb to 1.25v (nominal) through the dc/dc converter. if the fb input exceeds the regulation voltage, v fb , minus 50mv and the voltage between isp and isn has dropped below the c/10 threshold of 25mv (typical), the openled pull-down is asserted. this action may signal an open led fault. if fb is driven above the fb overvoltage threshold, the pwmout and gate pins will be driven low to protect the leds from an overcurrent event. do not leave the fb pin open. if not used, connect to gnd. i sn (pin 3): connection point for the negative terminal of the current feedback resistor. the constant output current regulation can be programmed by i led = 250mv/ r led when ctrl > 1.2v or i led = (ctrl C 100mv)/(4 ? r led ). if isn is greater than intv cc , input bias current is typically 20a flowing into the pin. below intv cc , isn bias current decreases until it flows out of the pin. isp (pin 4): connection point for the positive terminal of the current feedback resistor. input bias current depends upon ctrl pin voltage. when it is greater than intv cc it flows into the pin. below intv cc , isp bias current decreases until it flows out of the pin. if the difference between isp and isn exceeds 600mv (typical), then an overcurrent event is detected. in response to this event, the gate and pwmout pins are driven low to protect the switching regulator, a 1.5ma pulldown on pwm and a 9ma pulldown on the dim/ss pin are activated for 4s. v c (pin 5): transconductance error amplifier output pin used to stabilize the switching regulator control loop with an rc network. the v c pin is high impedance when pwm is low. this feature allows the v c pin to store the demand current state variable for the next pwm high transition. connect a capacitor between this pin and gnd; a resistor in series with the capacitor is recommended for fast transient response. ctrl (pin 6): current sense threshold adjustment pin. constant current regulation point v isp-isn is one-fourth v ctrl plus an offset for 0v ctrl 1v. for ctrl > 1.2v the v isp-isn current regulation point is constant at the full-scale value of 250mv. for 1v ctrl 1.2v, the dependence of v isp-isn upon ctrl voltage transitions from a linear function to a constant value, reaching 98% of full-scale value by ctrl = 1.1v. do not leave this pin open. v ref (pin 7): voltage reference output pin, typically 2v. this pin drives a resistor divider for the ctrl pin, either for analog dimming or for temperature limit/compensation of led load. it can be bypassed with 10nf or greater, or less than 50pf. can supply up to 185a (typical). pwm (pin 8): a signal low turns off switcher, idles the oscillator and disconnects the v c pin from all internal loads. pwmout pin follows the pwm pin, except in fault conditions. the pwm pin can be driven with a digital signal to cause pulse width modulation (pwm) dimming of an led load. the digital signal should be capable of sourcing or sinking 200a at the high and low thresholds. during start-up when dim/ss is below 1v, the first rising edge of pwm enables switching which continues until v isp-isn 25mv or ss 1v. connecting a capacitor from pwm pin to gnd invokes a self-driving oscillator where internal pull-up and pull-down currents set a duty ratio for the pwmout pin for dimming leds. the magnitude of the pull-up/down currents is set by the current in the dim/ss pin. the capacitor on pwm sets the frequency of the dimming signal. for hiccup mode response to output short-circuit faults, connect this pin as shown in the ap - plication titled boost led driver with output short-circuit protection. if not used, connect the pwm pin to intv cc . openled (pin 9): an open-drain pull-down on this pin asserts if the fb input is greater than the fb regulation voltage (v fb ) minus 50mv (typical) and the difference p in func t ions
lt3761 9 3761f p in func t ions between current sense inputs isp and isn is less than 25mv. to function, the pin requires an external pull-up resistor, usually to intv cc . when the pwm input is low and the dc/dc converter is idle, the openled condition is latched to the last valid state when the pwm input was high. when pwm input goes high again, the openled pin will be updated. this pin may be used to report transi - tion from constant current regulation to constant voltage regulation modes, for instance in a charger or current limited voltage supply. dim/ss (pin 10): soft-start and pwmout dimming signal generator programming pin. this pin modulates switching regulator frequency and compensation pin voltage (v c ) clamp when it is below 1v. the soft-start interval is set with an external capacitor and the dim/ss pin charging current. the pin has an internal 12a (typical) pull-up current source. the soft-start pin is reset to gnd by an undervoltage condition (detected at the en/uvlo pin), intv cc undervoltage, overcurrent event sensed at isp/ isn, or thermal limit. after initial start-up with en/uvlo, dim/ss is forced low until the first pwm rising edge. when dim/ss reaches the steady-state voltage (~1.17v), the charging current (sum of internal and external currents) is sensed and used to set the pwm pin charging and discharge currents and threshold hysteresis. in this manner, the ss charging current sets the duty cycle of the pwmout signal generator associated with the pwm pin. this pin should always have a capacitor to gnd, minimum 560pf value, when used with the pwmout signal generator function. place the pwm pin capacitor close to the ic. rt (pin 11): switching frequency adjustment pin. set the frequency using a resistor to gnd (for resistor values, see the typical performance curve or table 2). do not leave the rt pin open. place the resistor close to the ic. en/uvlo (pin 12): enable and undervoltage detect pin. an accurate 1.22v falling threshold with externally pro- grammable hysteresis causes the switching regulator to shut down when power is insufficient to maintain output regulation. above the 1.24v (typical) rising enable threshold (but below 2.5v), en/uvlo input bias current is sub-a. below the 1.22v (typical) falling threshold, an accurate 2.3a (typical) pull-down current is enabled so the user can define the rising hysteresis with the external resistor selection. an undervoltage condition causes the gate and pwmout pins to transition low and resets soft-start. tie to 0.4v, or less, to disable the device and reduce v in quiescent current below 1a. intv cc (pin 13): current limited, low dropout linear regula- tor regulates to 7.85v (typical) from v in . supplies internal loads, gate and pwmout drivers. must be bypassed with a 1f ceramic capacitor placed close to the pin and to the exposed pad gnd of the ic. v in (pin 14): power supply for internal loads and intv cc regulator. must be locally bypassed with a 0.22f (or larger) low esr capacitor placed close to the pin. sense (pin 15): the current sense input for the switch control loop. kelvin connect the sense pin to the positive terminal of the switch current sense resistor in the source of the external power nfet. the negative terminal of the switch current sense resistor should be kelvin connected to the exposed pad (gnd) of the lt3761. gate (pin 16): n-channel fet gate driver output. switches between intv cc and gnd. driven to gnd during shutdown, fault or idle states. gnd (exposed pad pin 17): ground. this pin also serves as current sense input for the control loop, sensing the negative terminal of the current sense resistor. solder the exposed pad directly to the ground plane.
lt3761 10 3761f b lock diagram + ? + ? + ? ? + ? + 1/4 a6 + + ? freq prog 1v 1v clamp 100mv ctrl v ref en/uvlo 25mv 185a 2.3a ctrl buffer current mode comparator driver pwm latch i sense a4 + ? 105mv g m a5 ovfb comparator 1.25v fb pwmout pwm pwmint 1.25v v in intv cc v c + ? + ? a2 r q s r q s ramp generator i dim_ss detect 100khz to 1mhz oscillator + ? + ? a8 7.85v ldo gate sense 3761 bd openled gnd 1.2v fb isn isp + ? 1.22v + ? 2.02v 1.3v fb 0.8v + f3(i dim/ss ) 0.8v rt dim/ss shdn cv eamp cc eamp a7 10a at fb = 1.25v 12a fault logic openled logic pwmint t > 165c isp > isn + 0.6v fault 10a bandgap reference ? + g m a1 a3 isn isp f1(i dim/ss ) f2(i dim/ss ) 10a at a1 + = a1 ? r led r sns i switch i led + ? + ? 1.5ma fault + ?
lt3761 11 3761f the lt3761 is a constant-frequency, current mode control - ler with a low side nmos gate driver. the gate pin and pwmout pin drivers and other chip loads are powered from intv cc , which is an internally regulated supply. in the discussion that follows it will be helpful to refer to the block diagram of the ic. in normal operation with the pwm pin low, the gate and pwmout pins are driven to gnd, the v c pin is high impedance to store the previous switching state on the external compensation capacitor, and the isp and isn pin bias currents are reduced to leakage levels. when the pwm pin transitions high, the pwmout pin transitions high after a short delay. at the same time, the internal oscillator wakes up and gener - ates a pulse to set the pwm latch, turning on the external power mosfet switch (gate goes high). a voltage input proportional to the switch current, sensed by an external current sense resistor between the sense and gnd input pins, is added to a stabilizing slope compensation ramp and the resulting switch current sense signal is fed into the negative terminal of the pwm comparator. the current in the external inductor increases steadily during the time the switch is on. when the switch current sense voltage exceeds the output of the error amplifier, labeled v c , the latch is reset and the switch is turned off. during the switch-off phase, the inductor current decreases. at the completion of each oscillator cycle, internal signals such as slope compensation return to their starting points and a new cycle begins with the set pulse from the oscillator. through this repetitive action, the pwm control algorithm establishes a switch duty cycle to regulate a current or voltage in the load. the v c signal is integrated over many switching cycles and is an amplified version of the differ - ence between the led current sense voltage, measured between isp and isn, and the target difference voltage set by the ctrl pin. in this manner, the error amplifier sets the correct peak switch current level to keep the led cur - rent in regulation. if the error amplifier output increases, more current is demanded in the switch; if it decreases, less current is demanded. the switch current is monitored during the on-phase and the voltage across the sense pin is not allowed to exceed the current limit threshold of 105mv (typical). if the sense pin exceeds the current limit threshold, the sr latch is reset regardless of the output state of the pwm comparator. the difference between isp and isn is monitored to determine if the output is in a short-circuit condition. if the difference between isp and isn is greater than 600mv (typical), the sr latch will be reset regardless of the pwm comparator. the dim/ss pin will be pulled down and the pwmout and gate pins forced low for at least 4s. these functions are intended to protect the power switch as well as various external components in the power path of the dc/dc converter. in voltage feedback mode, the operation is similar to that described above, except the voltage at the v c pin is set by the amplified difference of the internal reference of 1.25v and the fb pin. if fb is lower than the reference voltage, the switch current will increase; if fb is higher than the reference voltage, the switch demand current will decrease. the led current sense feedback interacts with the fb voltage feedback so that fb will not exceed the internal reference and the voltage between isp and isn will not exceed the threshold set by the ctrl pin. for accurate current or voltage regulation, it is necessary to be sure that under normal operating conditions the appropriate loop is dominant. to deactivate the voltage loop entirely, fb can be connected to gnd. to deactivate the led current loop entirely, the isp and isn should be tied together and the ctrl input tied to v ref . two led specific functions featured on the lt3761 are controlled by the voltage feedback pin. first, when the fb pin exceeds a voltage 50mv lower (C4%) than the fb regulation voltage, and the difference voltage between isp and isn is below 25mv (typical), the pull-down driver on the openled pin is activated. this function provides a status indicator that the load may be disconnected and the constant-voltage feedback loop is taking control of the switching regulator. the openled pin de-asserts only when pwm is high and fb drops below the voltage threshold. fb overvoltage is the second protective function. when the fb pin exceeds the fb regulation voltage by 60mv (plus 5% typical), the pwmout pin is driven low, ignoring the state of the pwm input. in the case where the pwmout pin drives a disconnect nfet, this action isolates the led load from gnd, preventing excessive current from damaging the leds. o pera t ion
lt3761 12 3761f a pplica t ions i n f orma t ion intv cc regulator bypassing and operation the intv cc pin requires a capacitor for stable operation and to store the charge for the large gate switching cur - rents. choose a 10v rated low esr, x7r ceramic capacitor for best performance. a 1f capacitor will be adequate for many applications. place the capacitor close to the ic to minimize the trace length to the intv cc pin and also to the ic ground. an internal current limit on the intv cc output protects the lt3761 from excessive on-chip power dissipation. the minimum value of this current should be considered when choosing the switching nmos and the operating frequency. i intvcc can be calculated from the following equation: i intvcc = q g ? f osc careful choice of a lower q g fet will allow higher switching frequencies, leading to smaller magnetics. the intv cc pin has its own undervoltage disable set to 4.1v (typical) to protect the external fets from excessive power dissipa - tion caused by not being fully enhanced. if the intv cc pin drops below the uvlo threshold, the gate and pwmout pins will be forced to 0v and the soft-start pin will be reset. if the input voltage, v in , will not exceed 8v, then the intv cc pin could be connected to the input supply. be aware that a small current (less than 13a) will load the intv cc in shutdown. this action allows the lt3761 to operate from v in as low as 4.5v. if v in is normally above, but occasionally drops below the intv cc regulation voltage, then the minimum operating v in will be close to 5v. this value is determined by the dropout voltage of the linear regulator and the intv cc undervoltage lockout threshold mentioned above. programming the turn-on and turn-off thresholds with the en/uvlo pin the power supply undervoltage lockout (uvlo) value can be accurately set by the resistor divider to the en/uvlo pin. a small 2.3a pull-down current is active when en/uvlo en/uvlo lt3761 v in r2 3761 f01 r1 figure 1. resistor connection to set v in undervoltage shutdown threshold is below the threshold. the purpose of this current is to allow the user to program the rising hysteresis. the fol- lowing equations should be used to determine the value of the resistors: v in,falling = 1.22 ? r1 + r2 r2 v in,rising = 2.3a ? r1 + v in,falling led current programming the led current is programmed by placing an appropriate value current sense resistor, r led , in series with the led string. the voltage drop across r led is (kelvin) sensed by the isp and isn pins. a half watt resistor is usually a good choice. to give the best accuracy, sensing of the current should be done at the top of the led string. if this option is not available then the current may be sensed at the bottom of the string, or in the source of the pwm disconnect nfet driven by the pwmout signal. a unique case of gnd sensing is the inverting converter shown in the applications where the led current is sensed in the cathode of the power schottky rectifier. this configuration allows the led anode to be grounded for heat sinking. in this case, it is important to lowpass filter the discontinu- ous current signal. input bias currents for the isp and isn inputs are shown in the typical performance characteristics and should be considered when placing a resistor in series with the isp or isn pins. the ctrl pin should be tied to a voltage higher than 1.2v to get the full-scale 250mv (typical) threshold across the sense resistor. the ctrl pin can also be used to dim the
lt3761 13 3761f a pplica t ions i n f orma t ion led current to zero, although relative accuracy decreases with the decreasing voltage sense threshold. when the ctrl pin voltage is less than 1v, the led current is: i led = v ctrl ? 100mv r led ? 4 when the ctrl pin voltage is between 1v and 1.2v the led current varies with ctrl, but departs from the previous equation by an increasing amount as the ctrl voltage increases. ultimately, the led current no longer varies for ctrl 1.2v. at ctrl = 1.1v, the value of i led is ~98% of the equations estimate. some values are listed in table 1. table 1. (isp-isn) threshold vs ctrl v crtl (v) (isp-isn) threshold (mv) 1.0 225 1.05 236 1.1 244.5 1.15 248.5 1.2 250 when ctrl is higher than 1.2v, the led current is regu - lated to: i led = 250mv r led the ctrl pin should not be left open (tie to v ref if not used). the ctrl pin can also be used in conjunction with a thermistor to provide overtemperature protection for the led load, or with a resistor divider to v in to reduce output power and switching current when v in is low. the presence of a time varying differential voltage signal (ripple) across isp and isn at the switching frequency is expected. the amplitude of this signal is increased by high led load current, low switching frequency and/or a smaller value output filter capacitor. some level of ripple signal is acceptable: the compensation capacitor on the v c pin filters the signal so the average difference between isp and isn is regulated to the user-programmed value. ripple voltage amplitude (peak-to-peak) in excess of fb lt3761 v out r4 3761 f02 r3 figure 2. feedback resistor connection for boost or sepic led driver fb lt3761 v out r4 100k 3761 f03 r3 led array r sen(ext) c out + ? 50mv should not cause mis-operation, but may lead to noticeable offset between the current regulation and the user-programmed value. programming output voltage (constant voltage regulation) or open led/overvoltage threshold for a boost or sepic application, the output voltage can be set by selecting the values of r3 and r4 (see figure?2) according to the following equation: v out = 1.25 ? r3 + r4 r4 figure 3. feedback resistor connection for buck mode or buck-boost mode led driver for a boost type led driver, set the resistor from the output to the fb pin such that the expected voltage level during normal operation will not exceed 1.17v. for an led driver of buck mode or a buck-boost mode configuration, the output voltage is typically level-shifted to a signal with respect to gnd as illustrated in figure 3. the output can be expressed as: v out = v be + 1.25 ? r3 r4
lt3761 14 3761f a pplica t ions i n f orma t ion isp/isn short-circuit protection feature the isp/isn pins have a protection feature independent of their led current sense feature. the purpose of this feature is to prevent the development of excessive cur - rents that could damage the power components or the load. the action threshold (v isp-isn > 600mv, typical) is above the default led current sense threshold, so that no interference will occur with current regulation. this feature acts in the same manner as switch current limit: it prevents switch turn-on until the isp/isn difference falls below the threshold. exceeding the threshold also activates a pull-down on the ss and pwm pins and causes the gate and pwmout pins to be driven low for at least 4s. if an overcurrent condition is sensed at isp/isn and the pwm pin is configured either to make an internal dimming signal, or for always-on operation as shown in the application titled boost led driver with output short protection, then the lt3761 will enter a hiccup mode of operation. in this mode, after the initial response to the fault, the pwmout pin re-enables the output switch at an interval set by the capacitor on the pwm pin. if the fault is still present, the pwmout pin will go low after a short delay (typically 7s) and turn off the output switch. this fault-retry sequence continues until the fault is no longer present in the output. pwm dimming control there are two methods to control the current source for dimming using the lt3761. one method uses the ctrl pin to adjust the current regulated in the leds. a second method uses the pwm pin to modulate the current source between zero and full current to achieve a precisely pro- grammed average current. to make pwm dimming more accurate, the switch demand current is stored on the v c node during the quiescent phase when pwm is low. this feature minimizes recovery time when the pwm signal goes high. to further improve the recovery time, a dis - connect switch may be used in the led current path to prevent the isp node from discharging during the pwm signal low phase. the minimum pwm on or off time is affected by choice of operating frequency and external component selection. the data sheet application titled boost led driver for 30khz pwm dimming demonstrates regulated current pulses as short as 3s are achievable. the best overall combina - tion of pwm and analog dimming capability is available if the minimum pwm pulse is at least six switching cycles. a low duty cycle pwm signal can cause excessive start-up times if it were allowed to interrupt the soft-start sequence. therefore, once start-up is initiated by pwm > 1.3v, it will ignore a logical disable by the external pwm input signal. the device will continue to soft-start with switching and pwmout enabled until either the voltage at ss reaches the 1v level, or the output current reaches one-tenth of the full-scale current. at this point the device will begin following the dimming control as designated by pwm. disconnect switch selection an nmos in series with the led string at the cathode is recommended in most lt3761 applications to improve the pwm dimming. the nmos bv dss rating should be as high as the open led regulation voltage set by the fb pin, which is typically the same rating as the power switch of the converter. the maximum continuous drain current i d(max) rating should be higher than the maximum led current. a pmos high side disconnect is needed for buck mode, buck-boost mode or an output short circuit protected boost. a level shift to drive the pmos switch is shown in the application schematic boost led driver with out- put short circuit protection. in the case of a high side disconnect follow the same guidelines as for the nmos regarding voltage and current ratings. it is important to include a bypass diode to gnd at the drain of the pmos switch to ensure that the voltage rating of this switch is not exceeded during transient fault events.
lt3761 15 3761f a pplica t ions i n f orma t ion pwm dimming signal generator the lt3761 features a pwm dimming signal generator with programmable duty cycle. the frequency of the square wave signal at pwmout is set by a capacitor c pwm from the pwm pin to gnd according to the equation: f pwm = 14khz ? nf/c pwm the duty cycle of the signal at pwmout is set by a a scale current into the dim/ss pin (see figure 4 and the typical performance characteristics). programming the switching frequency the rt frequency adjust pin allows the user to program the switching frequency (f sw ) from 100khz to 1mhz to optimize efficiency/performance or external component size. higher frequency operation yields smaller compo- nent size but increases switching losses and gate driving current, and may not allow sufficiently high or low duty cycle operation. lower frequency operation gives better performance at the cost of larger external component size. for an appropriate r t resistor value see table 2. an external resistor from the rt pin to gnd is requireddo not leave this pin open. table 2. switching frequency (f sw ) vs r t value f sw (khz) r t (k) 100 95.3 200 48.7 300 33.2 400 25.5 500 20.5 600 16.9 700 14.3 800 12.1 900 10.7 1000 8.87 duty cycle considerations switching duty cycle is a key variable defining converter operation, therefore, its limits must be considered when programming the switching frequency for a particular ap- plication. the minimum duty cycle of the switch is limited by the fixed minimum on-time and the switching frequency (f sw ). the maximum duty cycle of the switch is limited by the fixed minimum off-time and f sw . the following equations express the minimum/maximum duty cycle: min duty cycle = 220ns ? f sw max duty cycle = 1 C 170ns ? f sw dim voltage (v) 0 pwmout duty ratio (%) 100 60 20 80 40 0 2 6 4 3761 f04 8 c pwm = 47nf figure 4. pwmout duty ratio vs dim voltage for r dim = 124k internally generated pull-up and pull-down currents on the pwm pin are used to charge and discharge its capaci - tor between the high and low thresholds to generate the duty cycle signal. these current signals on the pwm pin are small enough so they can be easily overdriven by a digital signal from a microcontroller to obtain very high dimming performance. the practical minimum duty cycle using the internal signal generator is about 4% if the dim/ ss pin is used to adjust the dimming ratio. consult the factory for techniques for and limitations of generating a duty ratio less than 4% using the internal generator. for always on operation, the pwm pin should be connected as shown in the application boost led driver with output short protection.
lt3761 16 3761f a pplica t ions i n f orma t ion besides the limitation by the minimum off-time, it is also recommended to choose the maximum duty cycle below 95%. d boost = v led ? v in v led d buck _ mode = v led v in d sepic , d cuk = v led v led + v in thermal considerations the lt3761 is rated to a maximum input voltage of 60v. careful attention must be paid to the internal power dis- sipation of the ic at higher input voltages to ensure that a junction temperature of 125c (150c for h-grade) is not exceeded. this junction limit is especially important when operating at high ambient temperatures. if lt3761 junction temperature reaches 165c, the gate and pwmout pins will be driven to gnd and the soft-start (dim/ss) and pwm pins will be discharged to gnd. switching will be enabled after device temperature is reduced 10c. this function is intended to protect the device during momentary thermal overload conditions. the majority of the power dissipation in the ic comes from the supply current needed to drive the gate capacitance of the external power mosfet. this gate drive current can be calculated as: i gate = f sw ? q g a low q g power mosfet should always be used when operating at high input voltages, and the switching fre- quency should also be chosen carefully to ensure that the ic does not exceed a safe junction temperature. the internal junction temperature of the ic can be estimated by: t j = t a + [v in (i q + f sw ? q g ) ? ja ] where t a is the ambient temperature, i q is the quiescent current of the part (maximum 2ma) and ja is the package thermal impedance (43c/w for the mse package). for example, an application has t a(max) = 85c, v in(max) = 40v, f sw = 400khz, and having a fet with q g = 20nc, the maximum ic junction temperature will be approximately: t j = 85c + [40v ? (2ma + 400khz ? 20nc) ? 43c/w] = 102c the exposed pad on the bottom of the package must be soldered to a ground plane. this ground should then be connected to an internal copper ground plane with thermal vias placed directly under the package to spread out the heat dissipated by the ic. open led reporting C constant v oltage regulation status pin the lt3761 provides an open-drain status pin, openled, that pulls low when the fb pin is within 50mv of its 1.25v regulated voltage and output current sensed by v isp-isn has reduced to 25mv, or 10% of the full-scale value. the 10% output current qualification (c/10) is unique for an led driver but fully compatible with open led indication?C the qualification is always satisfied since for an open load, zero current flows in the load. the c/10 feature is particularly useful in the case where openled is used to indicate the end of a battery charging cycle and terminate charging or transition to a float charge mode. figure 5. typical minimum on and off gate pulse width vs temperature 0 100 200 300 50 150 250 3761 f05 time (ns) temperature (c) ?50 0 50 75 ?25 25 100 150125 minimum on-time minimum off-time c gate = 3300pf
lt3761 17 3761f figure 6. openled logic block diagram + ? 1.2v fb pwm 3761 f06 openled open led comparator c10 comparator 1ma isn 25mv isp 1. openled asserts when v isp-isn < 25mv and fb > 1.2v, and is latched 2. openled de-asserts when fb < 1.19v, and pwm logic 1 = 1v 3. any fault condition resets the latch, so lt3761 starts up with openled de-asserted r led i led + ? s q r + ? a pplica t ions i n f orma t ion for monitoring the led string voltage, if the open led clamp voltage is programmed correctly using the fb resistor divider then the fb pin should not exceed 1.18v when leds are connected. if the openled pulldown is asserted and the pwm pin transitions low, the pulldown will continue to be asserted until the next rising edge of pwm even if fb falls below the openled threshold. therefore, a 10f capacitor is an appropriate selection for a 400khz boost regulator with 12v input, 48v output and 1a load. with the same v in voltage ripple of 100mv, the input ca- pacitor for a buck converter can be estimated as follows: c in (f) = i led (a) ? t sw (s) ? 4.7 ? f a ? s ? ? ? ? ? ? a 10f input capacitor is an appropriate selection for a 400khz buck mode converter with a 1a load. in the buck mode configuration, the input capacitor has large pulsed currents due to the current returned through the schottky diode when the switch is off. in this buck converter case it is important to place the capacitor as close as possible to the schottky diode and to the gnd return of the switch (i.e., the sense resistor). it is also important to consider the ripple current rating of the capacitor. for best reliability, this capacitor should have low esr and esl and have an adequate ripple current rating. table 3. recommended ceramic capacitor manufacturers manufacturer web tdk www.tdk.com kemet www.kemet.com murata www.murata.com taiyo yuden www.t-yuden.com output capacitor selection the selection of the output capacitor depends on the load and converter configuration, i.e., step-up or step-down and the operating frequency. for led applications, the equivalent resistance of the led is typically low and the output filter capacitor should be sized to attenuate the current ripple. use of x7r type ceramic capacitors is recommended. to achieve the same led ripple current, the required filter capacitor is larger in the boost and buck-boost mode ap - plications than that in the buck mode applications. lower operating frequencies will require proportionately higher capacitor values. input capacitor selection the input capacitor supplies the transient input current for the power inductor of the converter and must be placed and sized according to the transient current requirements. the switching frequency, output current and tolerable input voltage ripple are key inputs to estimating the capacitor value. an x7r type ceramic capacitor is usually the best choice since it has the least variation with temperature and dc bias. typically, boost and sepic converters require a lower value capacitor than a buck mode converter. as - suming that a 100mv input voltage ripple is acceptable, the required capacitor value for a boost converter can be estimated as follows: c in (f) = i led (a) ? v out v in ? t sw (s) ? f a ? s ? ? ? ? ? ?
lt3761 18 3761f a pplica t ions i n f orma t ion soft-start capacitor selection for many applications, it is important to minimize the inrush current at start-up. the built-in soft-start circuit significantly reduces the start-up current spike and output voltage overshoot. connect a capacitor from the dim/ss pin to gnd to use this feature. the soft-start interval is set by the softstart capacitor selection according to the equation: t ss = c ss ? 1.2v 12a = c ss ? 100s nf provided there is no additional current supplied to the dim/ss pin for programming the duty cycle of the pwm dimming signal generator. a typical value for the soft-start capacitor is 10nf which gives a 1ms start-up interval. the soft-start pin reduces the oscillator frequency and the maximum current in the switch. the soft-start capacitor discharges if one of the follow- ing events occurs: the en/uvlo falls below its threshold; output overcurrent is detected at the isp/isn pins; ic overtemperature; or intv cc undervoltage. during start- up with en/uvlo, charging of the soft-start capacitor is enabled after the first pwm high period. in the start-up sequence, after switching is enabled by pwm the switch - ing continues until v isp-isn > 25mv or dim/ss > 1v. pwm pin negative edges during this start-up interval are not processed until one of these two conditions are met so that the regulator can reach steady state operation shortly after pwm dimming commences. power mosfet selection the selection criteria for the power mosfet includes the drain-source breakdown voltage (v ds ), the threshold voltage (v gs(th) ), the on-resistance (r ds(on) ), the gate to source and gate to drain charges (q gs and q gd ), the maximum drain current (i d(max) ) and the mosfets thermal resistances (r jc , r ja ). for applications operating at high input or output voltages, the power switch is typically chosen for drain voltage v ds rating and low gate charge q g . consideration of switch on-resistance, r ds(on) , is usually secondary because switching losses dominate power loss. the intv cc regula- tor on the lt3761 has a fixed current limit to protect the ic from excessive power dissipation at high v in , so the fet should be chosen so that the product of q g at 7.85v and switching frequency does not exceed the intv cc current limit. for driving leds be careful to choose a switch with a v ds rating that exceeds the threshold set by the fb pin in case of an open-load fault. the required power mosfet v ds rating of different topologies can be estimated using the following equations plus a diode forward voltage, and any additional ringing across its drain-to-source during its off-time. boost: v ds > v led buck mode: v ds > v in(max) sepic, inverting: v ds > v in(max) + v led since the lt3761 gate driver is powered from the 7.85v intv cc , the 6v rated mosfet works well for all the lt3761 applications. it is prudent to measure the mosfet temperature in steady state to ensure that absolute maximum ratings are not exceeded. several mosfet vendors are listed in table 4. the mosfets used in the application circuits in this data sheet have been found to work well with the lt3761. consult factory applications for other recommended mosfets. table 4. recommended power mosfet manufacturers manufacturer web vishay siliconix www.vishay.com infineon www.infineon.com renesas www.renesas.com
lt3761 19 3761f a pplica t ions i n f orma t ion schottky rectifier selection the power schottky diode conducts current during the interval when the switch is turned off. select a diode rated for the maximum sw voltage as described in the section on power mosfet selection. if using the pwm feature for dimming, it may be important to consider diode leakage, which increases with the temperature, from the output during the pwm low interval. therefore, choose the schottky diode with sufficiently low leakage current. table 5 has some recommended component vendors. the diode current and v f should be considered when select- ing the diode to be sure that power dissipation does not exceed the rating of the diode. the power dissipated by the diode in a converter is: p d = i d ? v f ? (1-d max ) it is prudent to measure the diode temperature in steady state to ensure that its absolute maximum ratings are not exceeded. table 5. schottky rectifier manufacturers manufacturer web vishay www.vishay.com central semiconductor www.centralsemi.com diodes, inc. www.diodes.com sense resistor selection the resistor, r sense , between the source of the exter - nal nmos fet and gnd should be selected to provide adequate switch current to drive the application without exceeding the 105mv (typical) current limit threshold on the sense pin of lt3761. for a boost converter, select a resistor value according to: r sense,boost v in ? 0.07v v led ? i led for buck-boost mode and sepic, select a resistor ac - cording to: r sense,buck-boost v in ? 0.07v v in + v led ( ) i led for buck mode, select a resistor according to: r sense,buck 0.07v i led these equations provide an estimate of the sense resistor value based on reasonable assumptions about induc- tor current ripple during steady state switching. lower values of sense resistor may be required in applications where inductor ripple current is higher. examples include applications with current limited operation at high duty cycle, and those with discontinuous conduction mode (dcm) switching. it is always prudent to verify the peak inductor current in the application to ensure the sense resistor selection provides margin to the sense current limit threshold. the placement of r sense should be close to the source of the nmos fet and gnd of the lt3761. the sense input to lt3761 should be a kelvin connection to the positive terminal of r sense . verify the power on the resistor to ensure that it does not exceed the rated maximum. inductor selection the inductor used with the lt3761 should have a saturation current rating appropriate to the maximum switch current selected with the r sense resistor. choose an inductor value based on operating frequency, input and output voltage to provide a current mode ramp on sense during the switch on-time of approximately 20mv magnitude. the following equations are useful to estimate the inductor value for continuous conduction mode operation (use the minimum value for v in and maximum value for v led ): l buck = r sense ? v led v in ? v led ( ) v in ? 0.02v ? f osc l buck-boost = r sense ? v led ? v in v led + v in ( ) ? 0.02v ? f osc l boost = r sense ? v in v led ? v in ( ) v led ? 0.02v ? f osc
lt3761 20 3761f a pplica t ions i n f orma t ion use the equation for buck-boost when choosing an in- ductor value for sepic C if the sepic inductor is coupled, then the equations result can be used as is. if the sepic uses two uncoupled inductors, then each should have a inductance double the result of the equation. table 6 provides some recommended inductor vendors. table 6. recommended inductor manufacturers manufacturer web coilcraft www.coilcraft.com cooper-coiltronics www.cooperet.com wrth-midcom www.we-online.com vishay www.vishay.com loop compensation the lt3761 uses an internal transconductance error amplifier whose v c output compensates the control loop. the external inductor, output capacitor and the compen - sation resistor and capacitor determine the loop stability. the inductor and output capacitor are chosen based on performance, size and cost. the compensation resistor and capacitor at v c are selected to optimize control loop response and stability. for typical led applications, a 4.7nf compensation capacitor at v c is adequate, and a series resistor should always be used to increase the slew rate on the v c pin to maintain tighter regulation of led current during fast transients on the input supply to the converter. the dc-coupling capacitor selection for sepic led driver the dc voltage rating of the dc-coupling capacitor c dc connected between the primary and secondary inductors of a sepic should be larger than the maximum input voltage: v cdc > v in(max) c dc has nearly a rectangular current waveform. during the switch off-time, the current through c dc is i vin , while approximately Ci led flows during the on-time. the c dc voltage ripple causes current distortions on the primary and secondary inductors. the c dc should be sized to limit its voltage ripple. the power loss on the c dc esr reduces the led driver efficiency. therefore, the sufficient low esr ceramic capacitors should be selected. the x5r or x7r ceramic capacitor is recommended for c dc . board layout the high speed operation of the lt3761 demands care - ful attention to board layout and component placement. figure?7 provides a suggested layout for the boost con - verter. the exposed pad of the package is the only gnd terminal of the ic and is also important for its thermal management. it is crucial to achieve a good electrical and thermal contact between the exposed pad and the ground plane of the board. to reduce electromagnetic interference (emi), it is important to minimize the area of the high dv/ dt switching node between the inductor, switch drain and anode of the anode of the schottky rectifier. use a ground plane under the switching node to eliminate interplane coupling to sensitive signals. proper layout of the power paths with high di/dt is es- sential to robust converter operation. the following high di/dt loops of different topologies should be kept as tight as possible to reduce inductive ringing: 1. in boost configuration, the high di/dt loop of each chan- nel contains the output capacitor, the sensing resistor, the power nmos and the schottky diode. 2. in buck mode configuration, the high di/dt loop of each channel contains the input capacitor, the sensing resistor, the power nmos and the schottky diode. 3. in buck-boost mode configuration, the high di/dt loop of each channel contains the capacitor connecting between v out and gnd, the sensing resistor, the power nmos and the schottky diode. 4. in sepic configuration, the high di/dt loop contains the power nmos, sense resistor, output capacitor, schottky diode and the dc-coupling capacitor.
lt3761 21 3761f a pplica t ions i n f orma t ion c ss m1 gnd pgnd agnd v in c in l1 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 4 3 3 2 1 5 6 1 2 r sense 7 8 r dim c c ctrl dim v ref r c v out via vias to ground planes layer 2 ground plane split openled x x r t r2 r1 r3 r4 r led 3761 f07 led + led ? m2 c out c out d1 component designations refer to boost led driver for automotive headlamp schematic cv cc c pwm pgnd agnd sense via x x figure 7. suggested layout of the boost led driver for automotive headlamp in the typical applications section the ground terminal of the switch current sense resistor should kelvin connect to the gnd of the lt3761. likewise, the ground terminal of the bypass capacitor for the intv cc regulator should be placed near the gnd of the switching path. typically this requirement will result in the external switch being closest to the ic, along with the intv cc bypass capacitor. the ground for the compensation network (v c ) and other dc control signals (e.g., fb, pwm, dim/ss, ctrl) should be star connected to the underside of the ic. do not extensively route high impedance signals such as fb and v c , as they may pick up switching noise. in particular, avoid routing fb and pwmout in parallel for more than a few millimeters on the board. minimize resistance in series with the sense input to avoid changes (most likely reduction) to the switch current limit threshold.
lt3761 22 3761f typical a pplica t ions 94% efficient boost led driver for automotive headlamp with 25:1 pwm dimming boost led driver with output short-circuit protection with externally driven pwm boost efficiency and output current vs v in v in lt3761 l1 10h rt v c intv cc en/uvlo fb v ref sense 1m 100k intv cc intv cc r1 499k c in 2.2f 2 100v c c 4.7nf c ss 0.01f c pwm 47nf 300hz c out 2.2f 4 v in 8v to 60v r dim 124k r2 90.9k r c 5.1k r t 28.7k 350khz c vcc 1f 140k ctrl r sense 10m m1 d1 m2 m1: infineon bsc123n08ns3-g d1: diodes inc pds5100 l1: coiltronics hc9-100-r m2: vishay siliconix si2328ds c out , c in : murata grm42-2x7r225k100r see suggested layout figure 7 (current derated for v in < 10v) r3 1m r4 16.9k 3761 ta02a openled dim/ss dim pwm gnd isp isn gate pwmout r led 0.25 1a 60w led string v in (v) 0 80 efficiency (%) 84 88 92 96 100 0.6 output current (a) 0.8 1.0 1.2 1.4 1.6 10 20 30 37551 ta02b 605040 output current pwm tied to intv cc efficiency q1 v in lt3761 l1 10h d1 rt v c intv cc en/uvlo fb v ref sense 1m 2.2k 1n4148 100k intv cc intv cc 499k 2.2f 2 100v 4.7nf 10nf 2.2f 4 100v v in 8v to 60v 90.9k 5.1k 28.7k 350khz 1f 140k ctrl 10m 1m m1 m2 16.9k 1k 1k 60w led string 3761 ta10 openled dim/ss pwm gnd isp isn gate pwmout 1a d2 q2 0.25 150pf 2.4k 27k 27k q3 m1: infineon bsc123no8ns3-g d1: diodes inc pds5100 l1: coiltronics hc9-100-r m2: vishay siliconix si7113dn d2: vishay 10bq100 q1, q3: central cmpt3906 q2: zetex fmmt493
lt3761 23 3761f typical a pplica t ions boost led driver with output short-circuit protection with internally generated pwm output short-circuit waveform showing hiccup mode operation with internally generated pwm high side disconnect internally generated pwm dimming waveform q1 v in lt3761 l1 10h d1 rt v c intv cc en/uvlo fb v ref sense 1m 28k 1n4148 124k 100k intv cc intv cc 499k 2.2f 2 100v 4.7nf 22nf 640hz 10nf 2.2f 4 100v v in 8v to 60v 90.9k 5.1k 28.7k 350khz 1f 140k ctrl 10m 1m m1 m2 led + 16.9k 1k 1k 60w led string current derated for v in < 10v 3761 ta09a openled dim/ss dim option for internally generated pwm dimming pwm gnd isp isn gate pwmout i led 1a d2 q2 m1: infineon bsc123no8ns3-g d1: diodes inc pds5100 l1: coiltronics hc9-100-r m2: vishay siliconix si7113dn d2: vishay 10bq100 q1: central cmpt3906 q2: zetex fmmt493 optional circuit for always-on operation 0.25 150pf 2.4k 20k v led + 0v 52v 1ms/div pwmout dim = 8v i led + 2a/div 3761 ta09c led + short to gnd i led 0.5a/div 10s/div pwmout 3761 ta09b v in = 24v, v led = 60v, dim = 0v
lt3761 24 3761f typical a pplica t ions 10w grounded anode inverting led driver 91m v in lt3761 l1 4.7h 1:1 rt v c en/uvlo isn pwm sense 2k 100k 4.7f 25v 4.7f 10v 42 13 0.1f 0.01f 1f v in 5v to 18v 2k 59k 20k 10 10 34k 28.7k 350khz 10nf fb 10m m1 d1 m2 ?10v clamp m1: vishay siliconix si4162dy (30v) d1: diodes pds1040 ctl l1: wrth 744870004 m2: vishay siliconix si2312bds (20v) led: cree xlamp xm-l q1: zetex fmmt593 10w led 3761 ta04a openled dim/ss intv cc gnd isp gate v ref ctrl pwmout 2.5a q1 ? ? 0.47f 2.2f 2 35v led ? pwm dimming waveform i led 1a/div v led ? 2v/div 10s/div pwm 3761 ta04b v in = 12v, v led = ?3.6v
lt3761 25 3761f v in (v) 0 efficiency (%) 10 20 30 37551 ta05b 40 80 84 88 92 100 96 0.6 output current (a) 0.9 1.2 1.5 1.8 2.1 output current efficiency typical a pplica t ions 40w sepic led driver sepic efficiency, output current vs v in v in lt3761 rt v c intv cc en/uvlo fb v ref sense 1m 100k intv cc intv cc 499k c1 2.2f 2 50v 4.7nf 10nf c3 10f 5 35v c2 2.2f 2 50v v in 8v to 40v 90.9k 10k 28.7k 350khz 1f 133k ctrl 8m 13 2 4 1m m1 m2 d1 49.9k 40w led string 3761 ta05a openled pwm dim/ss gnd isp isn gate pwmout 0.15 1.67a m1: infineon bsc123no8 d1: diodes inc pds5100 l1: coilcraft msd1278-103 m2: vishay siliconix si2306bds led: cree xlamp xm-l (7) c1, c2: kemet c1210c225k5 c3: taiyo yuden umk325bj106m l1 10h 1:1 ? ? pwm dimming waveform i led 0.5a/div 100s/div pwm 3761 ta05c
lt3761 26 3761f boost pwm dimming waveform i led 0.5a/div 5s/div pwm 3761 ta06b v in = 16v, v led = 30v i led 2a/div 5s/div pwm 3761 ta07b v in = 48v, v led = 38v typical a pplica t ions buck mode 5a led driver for 40khz pwm dimming boost led driver for 30khz pwm dimming buck mode pwm dimming waveform 1f 4.7nf 0.1f 3k 20.5k 500khz v in lt3761 l1 0.82h en/uvlo fb v ref sense 100k 187k c1 10f 25v c2 10f 2 35v v in 8v to 20v 39.2k ctrl 6m m1 d1 m2 499k 17.8k 3761 ta06a openled gnd isp isn gate pwmout 0.25 1a rt v c dim/ss pwm intv cc l1: vishay ihlp2525cz d1: diodes pds1040ctl m1: infineon bsc059n04 m2: vishay si2318cds 1f 4.7nf 0.1f 22k 16.9k 600khz v in lt3761 en/uvlo fb v ref isp sense gnd 100k 340k c2 2.2f 2 100v c1 4.7f 4 50v v in 44v to 80v 10k ctrl 50m 2w m1 up to 8 leds 4v to 40v 3761 ta07a openled isn gate m2 pwmout d2 5m 0.5w 5a rt v c dim/ss pwm intv cc l1 1h 158k 6.2v 0.22f 10k 2.2nf 200k 1m 200k d1 l1: wrth 744331010 m1: infineon bsc123no8ns3 m2: infineon bsc093no4ls d1: diodes pds5100 d2: central semi cmssh-3s c1: tdk c4532x7r1h475 c2: tdk c3225x7r2a225 led: cree xlamp xm-l (7) q1: zetex fmmt593 vishay q1
lt3761 27 3761f information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. p ackage descrip t ion please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. msop (mse16) 0911 rev e 0.53 0.152 (.021 .006) seating plane 0.18 (.007) 1.10 (.043) max 0.17 ?0.27 (.007 ? .011) typ 0.86 (.034) ref 0.50 (.0197) bsc 16 16151413121110 1 2 3 4 5 6 7 8 9 9 1 8 note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 6. exposed pad dimension does include mold flash. mold flash on e-pad shall not exceed 0.254mm (.010") per side. 0.254 (.010) 0 ? 6 typ detail ?a? detail ?a? gauge plane 5.23 (.206) min 3.20 ? 3.45 (.126 ? .136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.305 0.038 (.0120 .0015) typ 0.50 (.0197) bsc bottom view of exposed pad option 2.845 0.102 (.112 .004) 2.845 0.102 (.112 .004) 4.039 0.102 (.159 .004) (note 3) 1.651 0.102 (.065 .004) 1.651 0.102 (.065 .004) 0.1016 0.0508 (.004 .002) 3.00 0.102 (.118 .004) (note 4) 0.280 0.076 (.011 .003) ref 4.90 0.152 (.193 .006) detail ?b? detail ?b? corner tail is part of the leadframe feature. for reference only no measurement purpose 0.12 ref 0.35 ref mse package 16-lead plastic msop, exposed die pad (reference ltc dwg # 05-08-1667 rev e)
lt3761 28 3761f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com linear technology corporation 2012 lt 0812 ? printed in usa v in (v) 10 80 efficiency (%) 84 88 92 96 100 0.6 0.6 led current (a) 0.2 0.4 0.8 1.0 20 30 37551 ta03b 605040 led current pwm tied to intv cc efficiency r ela t e d p ar t s typical a pplica t ion part number description comments lt3755/lt3755-1/ lt3755-2 high side 40v, 1mhz led controller with true color 3000:1 pwm dimming v in : 4.5v to 40v, v out(max) = 75v, 3000:1 true color pwm dimming i sd < 1a, 3mm w 3mm qfn-16 and msop-16e packages lt3756/lt3756-1/ lt3756-2 high side 100v, 1mhz led controller with true color 3000:1 pwm dimming v in : 6v to 100v, v out(max) = 100v, 3000:1 true color pwm dimming i sd < 1a, 3mm w 3mm qfn-16 and msop-16e packages LT3796 high side 100v, 1mhz led controller with true color 3000:1 pwm dimming, pmos disconnect fet driver, input current limit and input/output current reporting v in : 6v to 100v, v out(max) = 100v, 3000:1 true color pwm dimming i sd < 1a, tssop-28e packages lt3956 high side 80v, 3.5a, 1mhz led driver with true color 3,000:1 pwm dimming v in : 6v to 80v, v out(max) = 80v, true color pwm dimming = 3000:1, i sd < 1a, 5mm w 6mm qfn-36 package lt3754 60v, 1mhz boost 16-channel 40ma led driver with true color 3000:1 pwm dimming and 2% current matching v in : 4.5v to 40v, v out(max) = 60v, true color pwm dimming = 3000:1, i sd < 1a, 5mm w 5mm qfn-32 package lt3518 2.3a, 2.5mhz high current led driver with 3000:1 dimming with pmos disconnect fet driver v in : 3v to 30v, v out(max) = 45v, 3000:1 true color pwm dimming, i sd < 1a, 4mm w 4mm qfn-16 and tssop-16e packages lt3478/lt3478-1 4.5a, 2mhz high current led driver with 3000:1 dimming v in : 2.8v to 36v, v out(max) = 40v, 3000:1 true color pwm dimming, i sd < 1a, tssop-16e package lt3791/lt3791-1 60v, synchronous buck-boost 700khz led controller v in : 4.7v to 60v, v out range: 0v to 60v, true color pwm, analog = 100:1, i sd < 1a, tssop-38e package 80w high voltage boost led driver with 25:1 internally generated pwm dimming hv boost efficiency and led current vs v in dimming waveform v in lt3761 rt v c intv cc en/uvlo fb v ref sense 590k 100k intv cc intv cc 187k 2.2f 2 100v 4.7nf 0.1f 10nf 1.4khz c out 0.22f 8 250v v in 12v to 60v 124k 21k 2k 39.2k 250khz 1f 20k ctrl 12m 1m 0805 8.66k 80w led string 135v max 3761 ta03a openled dim/ss dim 0v to 8v pwm gnd isp isn gate pwmout 0.39 650ma m1, m2: infineon bsc520n15 d1: diodes pds4150 l1: coiltronics hc9-220-r c out : tdk c3225x7r2e224k current derated for v in < 35v l1 22h m1 d1 m2 pwm (1v/div) i led (0.2a/div) 200s/div 3761 ta03c dim = 4v v in = 36v v led = 134v

▲Up To Search▲

Price & Availability of LT3796

	To Download LT3796 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .